//Stephen Kirksharian
//Robert Harkreader
//CPSC 321
//DUE 4/27/08

//Opcode cases
`define ADDIU 6'b001001
`define ADDI  6'b001000
`define ANDI  6'b001100
`define ORI   6'b001101
`define XORI  6'b001110
`define SLTI  6'b001010
`define SLTIU 6'b001011
`define LW    6'b100011
`define SW    6'b101011
`define BEQ   6'b000100
`define BNE   6'b000101
`define LB    6'b100000
`define SB    6'b101000
`define RTYPE 6'b000000

//Here are our control signals to send
`define SRTYP 4'b1111
`define ADD   4'b0000
`define ADDU  4'b0001
`define SUB   4'b0010
`define SUBU  4'b0011
`define AND   4'b0100
`define OR    4'b0101
`define XOR   4'b0110
`define SLT   4'b1010
`define SLTU  4'b1011
`define NOOP  4'b1111

module ALUop(opcodes,control);
	input [5:0] opcodes;
	output [3:0] control;
	reg [3:0] control;

always @(opcodes) begin
	#20 case(opcodes) 
	`RTYPE: control=`SRTYP;
	`ADDIU: control=`ADDU;
	`ADDI:  control=`ADD;
	`ANDI:  control=`AND;
	`ORI:   control=`OR;
	`XORI:  control=`XOR;
	`SLTI:  control=`SLT;
	`SLTIU: control=`SLTU;
	`LW:    control=`ADD;
	`SW:    control=`ADD;
	`BEQ:   control=`SUB;
	`BNE:   control=`SUB;
	`LB:    control=`ADD;
	`SW:    control=`ADD;
	endcase
end

endmodule